1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a method of driving a LCD device.
2. Discussion of the Related Art
Flat panel display (FPD) devices having portability and low power consumption have been subject of recent researches in the coming of the information age. Among the various types of FPD devices, liquid crystal display (LCD) devices are widely used as monitors for notebook computers and desktop computers because of their high resolution, ability to display colors and superiority in displaying moving images.
In general, a LCD device includes a first substrate, a second substrate and a liquid crystal layer between the first and second substrates. The LCD device uses the optical anisotropy and polarization properties of liquid crystal molecules to produce an image. Due to the optical anisotropy of the liquid crystal molecules, refraction of light incident onto the liquid crystal molecules depends upon the alignment direction of the liquid crystal molecules. The liquid crystal molecules have long thin shapes that can be aligned along specific directions. The alignment direction of the liquid crystal molecules can be controlled by applying an electric field. Accordingly, the alignment of the liquid crystal molecules changes in accordance with the direction of the applied electric field. Thus, by properly controlling the electric field applied to a group of liquid crystal molecules within respective pixel regions, a desired image can be produced by appropriately modulating transmittance of the incident light.
FIG. 1 is a schematic view showing a liquid crystal display device according to the related art. In FIG. 1, a LCD device includes a liquid crystal panel 100, a gate driver 120, a data driver 110, and a timing controller 130. A plurality of gate lines “GL1” to “GLn” and a plurality of data lines “DL1” to “DLm” are formed in the liquid crystal panel 100. The plurality of gate lines “GL1” to “GLn” and the plurality of data lines “DL1” to “DLm” cross each other to define a plurality of pixel regions “P.” A thin film transistor “T” is connected to the gate line and the data line, and a liquid crystal capacitor “LC” connected to the transistor “T” is formed in each pixel region. The charging of the liquid crystal capacitor is controlled by the ON/OFF state of the transistor “T,” thereby modulating transmittance of incident light.
When a gate signal is applied to a selected one of the plurality of gate lines “GL1” to “GLn,” the transistor “T” connected to the selected gate line is turned ON and a data signal applied to the plurality of data lines “DL1” to “DLm” is supplied to the liquid crystal capacitor “LC.” When a gate signal is not applied, the transistor is turned OFF and the liquid crystal capacitor “LC” keeps the charged data signal until the next frame. Even though not shown in FIG. 1, the liquid crystal capacitor “LC” may be defined by a pixel electrode on a first substrate, a common electrode on a second substrate and a liquid crystal layer between the pixel electrode and the common electrode. Furthermore, a storage capacitor (not shown) may be connected to the transistor to keep the charged data signal stable. Accordingly, an alignment state of liquid crystal molecules in the liquid crystal layer is controlled according to the charged data signal in the liquid crystal capacitor “LC,” thereby modulating the transmittance of incident light and displaying images.
The gate driver 120 receives control signals from the timing controller 130, and sequentially applies the gate signal to the plurality of gate lines “GL1” to “GLn” to turn ON transistor “T.” The data driver 110 receives control signals and an image signal from the timing controller 130, and supplies the data signal corresponding to one horizontal line to the plurality of data lines “DL1” to “DLm” in sync with the gate signal. The timing controller 130 receives the control signals and the image signal from an exterior circuit (not shown), and supplies the control signals and the image signal to the gate driver 120 and the data driver 110.
FIG. 2 is a schematic block diagram showing a gate driver of a liquid crystal display device according to the related art. In FIG. 2, a gate driver includes a shift register unit 210, a level shifter unit 220 and an output buffer unit 230. The shift register unit 210 receives a horizontal sync signal and a vertical sync signal and sequentially generates a scan pulse. The level shifter unit 220 receives the scan pulse and converts the scan pulse to a voltage level capable of driving transistor “T” (of FIG. 1). The output buffer unit 230 stabilizes the converted scan pulse and supplies the stabilized scan pulse to the plurality of gate lines “GL1” to “GLn” as a gate signal.
FIG. 3 is a schematic timing chart showing gate signals for a liquid crystal display device according to the related art. In FIG. 3, a sequential scan method is used for driving a plurality of gate lines. In a sequential scan method, a gate signal is applied to a selected gate line for a single horizontal time period “TL” and a plurality of gate signals are sequentially applied to the plurality of gate lines for a single horizontal time period.
As a LCD device increases in size, the number of gate lines and a resistance and a load capacitance of data lines increase. These increases reduce the time to charge a liquid crystal capacitor with image signals is reduced. As a result, a display quality of a LCD device is deteriorated due to a reduction in charge ratio.